1. Field of the Disclosure
The present disclosure generally relates to testing of electronic devices and, more particularly, to a system and method to test semiconductor memory chips.
2. Brief Description of Related Art
Memory devices are widely used in many electronic products and computers to store data. A memory device is a semiconductor electronic device that includes a number of memory cells, each cell storing one bit of data. The data stored in the memory cells can be read during a read operation. FIG. 1 is a simplified block diagram showing a memory chip or memory device 12. The memory chip 12 may be part of a DIMM (dual in-line memory module) or a PCB (printed circuit board) containing many such memory chips (not shown in FIG. 1). The memory chip 12 may include a plurality of pins 24 located outside of chip 12 for electrically connecting the chip 12 to other system devices. Some of those pins 24 may constitute memory address pins or address bus 17, data (DQ) pins or data bus 18, and control pins or control bus 19. It is evident that each of the reference numerals 17-19 designates more than one pin in the corresponding bus. Further, it is understood that the schematic in FIG. 1 is for illustration only. That is, the pin arrangement or configuration in a typical memory chip may not be in the form shown in FIG. 1.
A processor or memory controller (not shown) may communicate with the chip 12 and perform memory read/write operations. The processor and the memory chip 12 may communicate using address signals on the address lines or address bus 17, data signals on the data lines or data bus 18, and control signals (e.g., a row address select (RAS) signal, a column address select (CAS) signal, etc. (not shown)) on the control lines or control bus 19. The “width” (i.e., number of pins) of address, data and control buses may differ from one memory configuration to another.
Those of ordinary skill in the art will readily recognize that memory chip 12 of FIG. 1 is simplified to illustrate one embodiment of a memory chip and is not intended to be a detailed illustration of all of the features of a typical memory chip. Numerous peripheral devices or circuits may be typically provided along with the memory chip 12 for writing data to and reading data from the memory cells 26. However, these peripheral devices or circuits are not shown in FIG. 1 for the sake of clarity.
The memory chip 12 may include a plurality of memory cells 26 generally arranged in rows and columns to store data in rows and columns. A row decode circuit 28 and a column decode circuit 30 may select the rows and columns in the memory cells 26 in response to decoding an address, provided on the address bus 17. Data to/from the memory cells 26 is then transferred over the data bus 18 via sense amplifiers and a data output path (not shown). A memory controller (not shown) may provide relevant control signals (not shown) on the control bus 19 to control data communication to and from the memory chip 12 via an I/O (input/output) circuit 36. The I/O circuit 36 may include a number of data output buffers to receive the data bits from the memory cells 26 and provide those data bits or data signals to the corresponding data lines in the data bus 18. An exemplary I/O circuit is discussed below with reference to FIG. 2.
The memory controller (not shown) may determine the modes of operation of memory chip 12. Some examples of the input signals or control signals (not shown in FIG. 1) on the control bus 19 include an External Clock signal, a Chip Select signal, a Row Access Strobe signal, a Column Access Strobe signal, a Write Enable signal, etc. The memory chip 12 communicates to other devices connected thereto via the pins 24 on the chip 12. These pins, as mentioned before, may be connected to appropriate address, data and control lines to carry out data transfer (i.e., data transmission and reception) operations.
A test mode control unit 34 is also illustrated as part of the memory chip 12. The test mode control unit 34 may include digital logic such as, for example, one or more test mode registers to perform testing of the memory chip 12 to obtain information about various signals generated within the chip 12 as discussed later. A memory controller (not shown) may instruct the control unit 34 to supply the requested test mode related signal information from the chip 12.
FIG. 2 is a simplified diagram illustrating a portion of the I/O circuit 36 in the memory chip 12 shown in FIG. 1. The I/O circuit 36 is shown to include two signal processing circuits—an output driver unit 38, and an ODT (on die termination) circuit 40. Both of these signal processing circuits are shown connected to the data (DQ) pins 18 of the memory chip 12. The output driver 38 is shown to be directly connected to an external clock pin 42 (which is one of the pins 24 on the chip 12) to receive an output enable signal therethrough. However, in practice, there may be additional intervening circuits between the clock pin 42 and the output driver 38 to generate appropriate output enable signal to be supplied to the driver 38. The driver 38 also receives the data signals (DQ Out) 43 from the memory cells 26 to be output on the DQ pins 18 (e.g., during a memory read operation). Thus, the DQ Out signals 43 are generated internally within the chip 12 as shown in FIG. 2.
FIG. 3 illustrates an exemplary circuit layout of the output driver circuit 38. As is known in the art and as can be seen from FIG. 3, the DQ Out 43 signals are sent to the DQ pins 18 via the output driver 38 when the output enable signal 42 is active (e.g., active “high” in the implementation of FIG. 3). Once enabled, the output driver 38 provides necessary signal amplification and buffering to the data signals to be sent from the memory cells 26 to the DQ pins 18. There may be more than one output driver 38 in the memory chip 12—one output driver 38 for each data line 18. Each output driver 38 may have an IC (integrated circuit) output pad 46 to convey the data signals to the corresponding DQ pins 18 as is known in the art. It is noted here that, for the sake of simplicity, the reference numeral “42” is used to interchangeably refer to the clock pin and the output enable signal. In practice, the clock input at pin 42 may not directly be used as the output enable signal, but may get processed through intervening digital logic (not shown) to obtain the output enable signal as is known in the art.
Referring again to FIG. 2, it is seen that the I/O circuit may also include the on-chip ODT circuit 40 to improve signal integrity in the system. An ODT pin 44 (one of the pins 24 on the chip 12) may be provided on the chip to receive an externally-supplied (e.g., by a memory controller) ODT enable signal to activate the ODT circuit 40. Although the ODT circuit 40 in FIG. 2 is shown connected to the DQ pins 18, in practice, corresponding ODT circuits 40 may be provided for any other pins on the chip 12 including, for example, the address pins 17 and the control pins 19. The ODT circuit 40 may be more prevalent in DDR (Double Data Rate) SDRAMs (Synchronous Dynamic Random Access Memories).
In operation, the ODT circuit 40 provides desired termination impedance to improve signal integrity by controlling reflected noise on the transfer line connecting the memory chip 12 to another processing device, e.g., a memory controller (not shown). In a DDR SDRAM, the termination register (not shown) that was conventionally mounted on a motherboard carrying memory chips is incorporated inside the DDR SDRAM chip (e.g., as part of the test mode control unit 34) to enable or disable the ODT circuit 40 when desired. The termination register may be programmed through the ODT pin 44 by an external processor (e.g., a memory controller) to enable/disable the ODT circuit 40. As is known in the art, for example, when two memory chips 12 are loaded in a system, then during a memory write operation to one of the chips 12, the ODT circuit 40 in the other chip (which is not receiving data) is activated to absorb any signal propagations or reflections received on the data lines 18 (or address or control lines) of that “inactive” chip. This selective activation/deactivation of the ODT circuit 40 (e.g., in the memory chip that is not currently sending or receiving data) prevents the “inactive” chip from receiving spurious signals, thereby avoiding data corruption in the chip. The ODT circuit 40 thus improves signal (e.g., data signals) integrity in the memory chip 12.
FIG. 4 depicts an exemplary circuit diagram of the ODT circuit 40. The ODT circuit 40 may include two identical termination resistors RT 48-49 whose values may be adjusted (e.g., by the external memory controller (not shown) through programming of the termination register (not shown)) depending on the desired termination. Thus, the termination resistors RT 48-49 may not be strictly passive, fixed-value resistors. It is known that the termination value of RT 48-49 may be equal to the Thevenin equivalent of the resistors that terminate the DQ pins 18 at the IC output pad 52. The ODT circuit 40 may also include two switching elements—the “pull-up” n-channel CMOS transistor 50 and the “pull-down” n-channel CMOS transistor 51. Proper biasing for the ODT circuit 40 may be provided as indicated and as is known in the art. As mentioned earlier, the ODT circuit 40 is activated when the ODT Enable signal 44 goes “high” (in the implementation of FIG. 4) and deactivated when the signal 44 is in the “low” state. It is observed that, for the sake of simplicity, the reference numeral “44” is used to interchangeably refer to the ODT pin and the ODT Enable signal. In practice, the signal received on the ODT pin may be processed by intervening logic circuitry (not shown) to generate the desired ODT Enable signal.
FIG. 5 shows an exemplary block diagram illustrating how a test mode related signal 56 is traditionally output to the DQ pins 18 of the memory 12 in FIG. 1. In the discussion hereinbelow, the term “test mode related signal” is used to refer to any signal present on chip or on the die of an electronic device (e.g., the memory chip 12) and which is desired to be monitored by an external controller (e.g., a processor or memory controller (not shown)) during testing of the operation of the electronic device. For convenience, such signal is referred to by letter “A” in the discussion below. It is noted here that the information transfer during the testing operation is distinct from and may not be part of the routine data transfer during typical memory read/write operations. The test mode related signals 56 may include various data outputs (DQ Out 43), output from one or more redundant elements on the chip 12 (e.g., a redundant row of memory cells to replace a current row of memory cells when one or more cells in the current row are defective, or a redundant column of memory cells, etc.), signals generated by a DLL (delay locked loop) or other clock generation circuits on the chip, various control signals such as shift left (SL), shift right (SR), Reset, DLL coarse shift, DLL fine shift, etc. These signals may need to be monitored in the event of a malfunction of the chip 12, to debug the chip functionality or to ascertain operational defects in the chip 12 during testing of the chip.
Traditionally, a test mode related signal 56 is output over DQ pins 18 to an “inquiring” device (e.g., the test processor or memory controller (not shown)) via the corresponding output driver circuit 38 as shown in FIG. 5. The test processor or memory controller (not shown) may instruct the test mode control unit 34 to enable the output driver 38 to propagate appropriate signal “A” to the data output pins 18. Although circuit details of such test mode signal transfers in FIG. 5 are not shown here, it is observed that one or more signals from the control unit 34 and the signal “A” 56 may be processed through a digital circuit (not shown) prior to being applied to the output driver 38 to be output to the DQ pins 18.
In the arrangement of FIG. 5, to communicate internal chip signals to an outside controller (e.g., a memory controller (not shown)), the use of various corresponding output drivers 38 and testing related circuitry coupled to these drivers 38 results in addition of capacitance to the external pins 24 (e.g., DQ pins 18) through which signals “A” 56 are obtained. Also, such “loading” of output drivers 38 by testing related logic circuitry negatively affects chip performance during routine high speed data transfer operations (e.g., typical memory read/write operations during run time). For example, more gates added to output drivers 38 for testing related circuitry may not only result in additional output delays, but may also cause jitter on output signals and may significantly deteriorate quality of output signals. Furthermore, as clock speed of electronic devices (e.g., memory chips) increases, any addition of test mode-specific output drivers—i.e., output drivers dedicated to transmit only signals “A” 56—as part of the I/O circuit 36 on the chip 12 would result in additional capacitive loading at the DQ pins 18 used for test mode related signal transfers, thereby further affecting the speed with which output can be obtained. The on chip placement of such extra output drivers would also result in unnecessary waste of chip real estate.
Therefore, it is desirable to devise a test mode related signal transfer mechanism that does not add capacitance to output pins and also not affect the output speed path of signals output from the electronic device. It is further desirable to obtain such signal transfer mechanism without significantly adding logic circuitry on the chip real estate.